This application is based upon and claims the benefit of Japanese Patent Application No. 2001-374256 filed on Dec. 7, 2001, the contents of which are incorporated herein by reference.
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device with a peripheral portion for withstanding a surge voltage.
Conventionally, a semiconductor device including an IGBT or the like has a peripheral portion for withstanding a surge voltage (e.g., JP-A-10-163482).
FIG. 5 shows a cross sectional view of such a semiconductor device with an IGBT. IGBT elements (hereinafter referred to as a cell portion) are formed on a right side of the device in FIG. 5. A peripheral portion for withstanding a surge voltage caused by power surge (hereinafter referred to as a peripheral voltage withstand portion) is formed on a left side of the cell portion.
A semiconductor substrate 101 includes a p+ type layer 101A and an nxe2x88x92 type layer 101B disposed on the p+ type layer 101A. A side of the p+ type layer 101A of the semiconductor substrate 101 is a reverse surface 101a on which a collector electrode 102 is formed, and a side of the nxe2x88x92 type layer 101B is a main surface 101b. 
In the peripheral voltage withstand portion, a peripheral p type well region 113 is formed on a surface portion of the nxe2x88x92 type layer 101B. A p type well region 114, which is shallower than the peripheral p type well region 113, is formed at the most peripheral position of the peripheral p type well region 113 so as to overlap therewith. Hereinafter, the p type well region 114 is referred to as a most peripheral well region. In a most peripheral position of the semiconductor device, an n+ region 115 is formed on the surface portion of the nxe2x88x92 layer 101B to surround the cell portion and the most peripheral well region 114.
A LOCOS oxide film 116 is formed on the main surface 101b of the nxe2x88x92 type layer 101B and a plurality of field plate rings 117a-117e formed thereon are disposed from the peripheral p type well region 113 to an edge of the n+ type region 115 on a side of the cell portion. Zener diodes 118a-118d made of poly-silicon or the like are disposed on the field plate rings 117a-117e. Each of the zener diodes 118a-118d is disposed between and electrically contacts adjacent field plate rings 117a-117e. The field plate ring 117a is electrically connected to a gate electrode 119, and the field plate ring 117e is electrically connected to the n+ region 115.
In the above semiconductor device, each of the field plate rings 117a-117e and each of the Zener diodes 118a-118d are alternatively disposed at predetermined intervals in the cell portion to a periphery of the cell portion. Therefore, in the nxe2x88x92 type layer 101B, an electric potential is distributed uniformly in a direction from the peripheral p type well region 113 to the most peripheral well region 114 when a surge voltage is applied to the semiconductor device. The surge voltage applied to the semiconductor device is distributed along a surface of the nxe2x88x92 type layer 101B, and therefore an electric field is prevented from being locally concentrated.
Further, in the above semiconductor device, the most peripheral well region 114 with a shallow and relatively low impurity concentration is located at a periphery of the peripheral p type well region 113, and the field plate ring 117a located at the innermost side of the field plate rings 117a-117e protrudes from a peripheral edge 14aE of the most peripheral well region 114 in a peripheral direction. Accordingly, curvature of a peripheral edge of the peripheral p type well region 113 and an electric field distribution feature near the edge is improved, and local concentration of the electric field is prevented.
FIG. 6A shows an equipotential line distribution of a cross section of the semiconductor device of FIG. 5 calculated based on a simulation analysis. FIG. 6B shows an expansion view of a region B near a peripheral edge 117aE of the field plate ring 117a of FIG. 6A. In the simulation, dV/dt is about 2 kV/ns. When a reverse bias is applied to the semiconductor device, a depletion layer formed by a PN junction of the nxe2x88x92 type layer 101B and the peripheral p type well region 113 extends in a side of the peripheral p type well region 113 from the PN junction. Since the depletion layer extends from the peripheral p type well region 113 in a further peripheral direction thereof, the equipotential line distributes as in FIG. 6A based on the electric potential of the field plate rings 117a-117e. 
However, as shown in FIG. 6B, because the peripheral edge 114aE of the most peripheral well region 114 separates from the field plate ring 117a and the field plate ring 117b neighboring the field plate ring 117a, the equipotential line extends from the most peripheral well region 114 and the peripheral p type well region 113 to the portion disposed between both field plate rings 117a, 117b along the LOCOS oxide layer 116. Therefore, the equipotential line concentrates in a part of the LOCOS oxide film 116 under the peripheral edge 117aE of the field plate ring 117a, and an electric field intensity increases at the part of the LOCOS oxide film 116. Accordingly, reliability of the LOCOS oxide film 116 for withstanding the surge voltage, especially a rapid surge voltage, may decrease.
It is therefore an object of the present invention to provide a semiconductor device that is capable of obviating the above problem.
It is another object of the present invention to provide a semiconductor device with an oxide film having increased reliability for withstanding surge voltage.
According to a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of the field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings neighboring the first plate ring.
As the first semiconductor region is not completely depleted by a depletion layer, it is preferable that an edge of the depletion layer extended to the first semiconductor layer is located between or near the first field plate ring and the second field plate ring. Further, when a reduced surface field (resurf) configuration is connected to the periphery of the first semiconductor region, the peripheral edge of the first semiconductor layer can be defined by correlating it to a position located between a first field plate ring and the second field plate ring.
Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding surge voltage increases.